A frequency divider enables a frequency division of an input signal with a known division ratio, in order to obtain a signal having a desired frequency.
Frequency dividers are employed for example in radio frequency (RF) front-ends used for wireless data transmissions, and more specifically in phase-locked loop (PLL) architectures of frequency synthesizers of such RF front-ends.
Conventional frequency dividers include a dual-modulus prescaler and two programmable counters. The respectively required division ratio is set by programming the counters.
As described in the document ‘A Family of Low-Power Truly Modular Programmable Dividers in Standard 0.35-μm CMOS Technology’, IEEE Journal of solid-state circuits, vol. 35, No. 7, July 2000, by Cicero S. Vaucher, Igor Ferencic, Matthias Locher, Sebastian Sedvallson, Urs Voegeli and Zhenhua Wang, such conventional frequency dividers have several disadvantages, though.
A frequency divider making use of counters is not based on a modular concept. Moreover, the counters represent a substantial load at the output of the dual-modulus prescaler, which results in a high power consumption of the frequency divider. This is of particular disadvantage when the frequency divider is to be used in mobile devices. Further, the use of counters in addition to a prescaler implies a higher effort for design and layout of the frequency divider.
In the cited document ‘A Family of Low-Power Truly Modular Programmable Dividers in Standard 0.35-μm CMOS Technology’, it is therefore proposed to use instead a modular frequency divider which is based on 2/3 divider cells.
The basic architecture of such a modular frequency divider is illustrated in the block diagram of FIG. 1.
The frequency divider comprises n 2/3 divider cells 15-1, 15-2, 15-3, . . . , 15-n arranged in a chain, where n is a natural number. The frequency divider enables a programmable division of an input frequency. Each divider cell 15-1 to 15-n includes to this end two functional blocks (not shown).
The first functional block of a divider cell 15-x is a prescaler logic block, which divides the frequency of an input signal and which outputs a frequency divided signal Fx, where x=1 to n is the ordinal number of a respective divider cell. For the frequency division, the prescaler logic block can use a division ratio of two or a division ratio of three. The signal Fx output by the n−1 first divider cells 15-x=15-1 to 15-(n−1) is provided to the respective next divider cell 15-(x+1)=15-2 to 15-(n) in the divider chain.
The second functional block of a divider cell 15-1 to 15-n is an end-of-cycle logic block, which determines the division ratio to be used by the prescaler logic block of the same divider cell. The end-of-cycle logic block of each divider cell 15-1 to 15-n receives a dedicated control signal p0 to pn−1 via a programming input. The end-of-cycle logic block of the last divider cell 15-n in the divider chain receives in addition a fixed end-of-cycle signal modn via a feedback input. The end-of-cycle logic block of all other divider cells 15-x, with x=1 to (n−1), receives in addition via a feedback input an end-of-cycle signal modx output by the end-of-cycle logic block of the respective next divider cell 15-(x+1) in the divider chain.
The divider cells 15-1 to 15-n are programmed by setting the division ratio control signals p0 to pn−1.
During a division operation, the first divider cell 15-1 receives an input signal Fin and provides a frequency divided signal F1 to the second divider cell 15-2. Each further divider cell 15-x, with x=2 to n, receives a signal Fx−1 from the respective preceding divider cell 15-(x−1) in the division chain and outputs a further frequency divided signal Fx. By default, each divider cell 15-1 to 15-n divides an input signal by two.
Upon completion of a division cycle, however, the last divider cell 15-n in the divider chain generates an end-of-cycle signal modn−1, which propagates with each clock cycle of a respective input signal Fx to a respective preceding divider cell 15-x as an end-of-cycle signal modx, with x=n−1 down to 1. The term division cycle refers to the current clock period of the signal Fn output by the last divider cell 15-n. The signal modn−1 forms at the same time the output signal Fout of the frequency divider.
When the end-of-cycle signal modx becomes active at the feedback input of an end-of-cycle logic block, the end-of-cycle logic block controls the prescaler logic block of the same divider cell 15-x in a way that the division ratio applied by the prescaler logic block is two or three. An active signal modx at the feedback input enables a divider cell 15-x to divide the frequency of an input signal Fx−1 once by three, provided that the control signal px at the programming input is set to ‘1’. Otherwise, a division by two is carried out as before.
By choosing appropriate control signals p0 to pn−1 for the divider cells 15-1 to 15-n of the divider chain, the total division ratio of the frequency divider can thus be set to a desired value.
The presented modular frequency divider offers various advantages when used for an Integer-N division, that is, for a division of an available frequency by an integer factor N. The modular approach and the easy optimization for a low power consumption allow using this divider architecture in Integer-N PLL architectures of frequency synthesizers.
However, while this modular frequency divider is well suited for an Integer-N PLL operation, it is not suited for a Fractional-N PLL operation, in which an available frequency is to be divided by a fractional factor N.
In an Integer-N division, the division ratio control signals are adjusted once for a desired output frequency. These division ratio control signals can then be maintained until another output frequency is desired. For a Fractional-N division, in contrast, the division ratio control signals have to be varied repeatedly for achieving the desired output frequency.
A Fractional-N PLL requires more specifically a frequency divider that is able to switch the division ratio for each division cycle without latency. This is necessary, because a delta-sigma modulator, which usually provides the division ratio control signals for a frequency divider inside a Fractional-N PLL, changes the control signals after each period of a reference frequency representing the desired output frequency. In a Fractional-N mode, the division ratio will thus be changed during a respective division cycle. This poses the problem that the division is performed with the old division ratio in divider cells that have been passed in the division cycle, and with the new division ratio in divider cells that will only be passed after the change of the control signals. The result is an invalid division ratio for the current division cycle.
Therefore, mostly the conventional frequency dividers, consisting of a multi-modulus prescaler and two counters, are still used for realizing a Fractional-N PLL of a frequency synthesizer.